Description:
PCS Error insertion configuration.
Parents: Port
| Attribute | Description | ||||||
|---|---|---|---|---|---|---|---|
| Common Writable Attributes | Active, Name | ||||||
| Bip3 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| Bip7 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| BurstCount |
Number of error bursts. Type: u64 Default: 1 Range: 1 - 0x3fffffffffff |
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| BurstInterval |
Blocks between each error burst. Type: u32 Default: 1 |
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| BurstLength |
Sequential errored blocks in each burst. Type: u32 Default: 1 Range: 1 - 0xffffff |
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| ContinuousMode |
Boolean flag to indicate whether the PCS Error insertion is continuous or not. Type: bool Default: TRUE Possible Values:
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| ErrorInsertionMode |
Indicates if only alignment markers or every payload block should be corrupted on error insertion. Type: enum Default: LANE_MARKERS_ONLY Possible Values:
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| LaneEnable |
Boolean flags to individually enable each of the lanes for PCS Error insertion. Type: bool Default: FALSE Possible Values:
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| Marker0 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| Marker1 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| Marker2 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| Marker4 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| Marker5 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| Marker6 |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 255 |
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| SyncHeader |
Alignement Marker bytes (to corrupt) The transmitters periodically insert alignment markers simultaneously on all PCS lanes after the transmission of every 16,383 blocks of data and control. Non-zero value for any bit would indicate that the bit should be flipped (corrupted) upon transmission. Type: u8 Default: 0 Range: 0 - 3 |
There are no read-only attributes.